Master-slice system semiconductor integrated circuit and design method thereof

ABSTRACT

A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice  100  having a plurality of basic cells  110  formed in a matrix, in which first and second power source wirings  170  and  171  that traverse the plurality of basic cells  110  are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells  110  and/or between the plurality of basic cells  110 . The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list. The registered effective pin positions are provided on lattice grids  120 , located inside and outside a region between the first and second power source wirings  170  and  171 . In the circuit wired according to the definitions, contacts with respect to the drains are provided inside and outside the region between the first and second power source wirings  170  and  171 , and the signal wirings do not cross the power source wirings.

FIELD OF THE INVENTION

The present invention relates to a master slice type semiconductorintegrated circuit, such as a gate array or an embedded array, and amethod for manufacturing the same. More particularly, the presentinvention relates to improvements in making the effective use of wiringresources.

TECHNICAL BACKGROUND

Master slice type semiconductor integrated circuits, such as, forexample, gate arrays and embedded arrays, are manufactured using anunfinished wafer (master slice) in which those process steps to beperformed before the metal wiring step are completed. The master sliceis wired according to specific circuit functions required by the userand coated with a protection film, to thereby provide a finished wafer.Unfinished wafers may be stocked such that the delivery time isshortened to deliver semiconductor integrated circuits to customers.

Prior to manufacturing master slice type semiconductor integratedcircuits, an unfinished wafer having basic cells arranged in a matrix isprepared in advance. Provision of through holes and placement and wiringof metal wiring layers to the unfinished wafer are automaticallyperformed by an automatic placing and routing apparatus.

There is a growing tendency in which the number of metal wiring layersis increased, for example, from the two-layer to the three-layer and tothe four-layer. The bottommost or first metal wiring layers in asemiconductor integrated circuit of the type described above are used assignal input wirings for inputting signals to gates of MOS transistorsthat form basic cells, power supply wirings for supplying power tosources thereof and signal output wirings for outputting signals fromdrains thereof, for example. These wirings are connected to the gates,sources or drains through contacts. Also, first metal wiring layers maybe used as power source wirings for supplying power source voltages,such as potentials VDD and VSS, and signal wirings that provideconnections within basic cells and between basic cells. Other metalwiring layers, such as second and third metal wiring layers, are usedmainly as signal wirings.

Aluminum layers are generally used as metal wiring layers. For example,a two-layer metal wiring layer may include a first A1 wiring and asecond A1 wiring. When wiring routes of the first and second A1 layersare determined by an automatic placing and routing apparatus, prioritywiring directions are respectively assigned to the first and second A1wirings.

It is noted that it is more difficult to miniaturize a master slice typesemiconductor integrated circuit having a plurality of metal wiringlayers compared to a standard cell type that is designed using basiccells registered in a library.

For example, let us consider one wiring example in which a signal wiringis externally lead out from a region between two power source wirings inthe first layer (VDD, VSS) that are formed in a first priority wiringdirection, for example. In this case, if the two power source wiringsand the signal wiring are formed with the first layers, they areshort-circuited. In order to cross over the power source wirings formedin the first priority wiring direction, the signal wiring has to beformed with a first layer signal wiring, a second layer signal wiringand a via that connects the first and second layer signal wirings. Thesecond layer signal wiring is used only to cross over the first powersource wiring. As a consequence, other wirings cannot be formed in sucha region in the second layer. The other wirings in the second layer mayneed to take a detour. In this manner, the routing resource for thesecond layer is exhausted.

For the convenience of explanation, let us assume, for example, thereare 100 lateral lines×100 vertical lines of lattice grids in athree-layer metal wiring structure, and the priority wiring directionfor the first and third layers is the lateral direction and the prioritywiring direction for the second layer is the vertical direction. In thiscase, while the first and third layers provide a total of 200 wiringlines in the lateral direction as the routing resource, the second layerprovides 100 wiring lines in the vertical direction as the routingresource.

It is noted that the placement of the metal wirings in the first layeris mostly determined by the placement of basic cells, and the number ofusable wiring lines is determined as a matter of course. Therefore, ifthe wirings in the second and third layers are disposed in awell-balanced manner, the size of the chip can reduced. However, asdescribed above, if the wirings in the second layer are used to crossover the wirings in the first layer, the wiring efficiency of the secondlayer deteriorates.

In addition, when a roundabout routing of wirings is implemented byconnecting a plurality of layers with vias, or a roundabout routing ofwirings is made within the same layer, the wiring length increases.Moreover, in recent years, the line width has become narrower as thesemiconductor manufacturing process has become more miniaturized. As aresult, the resistance of the wiring per unit length tends to increase.Because of these two major factors, problems arise in that the wiringresistance is increased, and the signal delay is thus increased.

In solving these problems, the inventors of the present application havepaid attention to the fact that the wiring resource of metal wiringlayers and, in particular, the wiring resource of second metal wiringlayers are not effectively utilized.

It is an object of the present invention to provide a master slice typesemiconductor integrated circuit and a design method therefor that makean effective use of the wiring resource of metal wiring layers tothereby increase the wiring efficiency and reduce the chip size.

Another object of the present invention is to provide a master slicetype semiconductor integrated circuit and a design method therefor thatprevent the increase in the wiring resistance and reduce the signaldelay as much as possible by making an effective use of the wiringresource of metal wiring layers to thereby increase the wiringefficiency.

SUMMARY OF THE INVENTION

In accordance with one embodiment of the present invention, a placingand wiring method for a master slice type semiconductor integratedcircuit is provided. The method is conducted by an automatic placing androuting apparatus with respect to a master slice having a plurality ofbasic cells formed in a matrix, in which first and second power sourcewirings that are formed along a first direction and traverse theplurality of basic cells are connected to a plurality of signal wiringsthat are formed along the first direction or a second direction thattraverse the first direction to wire within each of the plurality ofbasic cells and/or between the plurality of basic cells.

The method according to the embodiment includes: the first step ofregistering in the automatic placing and routing apparatus that definesthe first direction or the second direction as a priority wiringdirection definitions of effective pin positions that connect theplurality of signal wirings, the plurality of first and second powersource wirings and the plurality of basic cells for each of layers inwhich the wirings are formed; the second step of registering a net listthat defines connections among the plurality of basic cells in theautomatic placing and routing apparatus; and the third step ofdetermining the placement of actual pin positions and wiring routes forthe first and second power source wirings and the plurality of signalwirings based on data for the definitions of the effective pin positionsand the net list.

The first step includes the step of defining the effective pin positionsinside and outside of a region between the first power source wiring andthe second power source wiring, in a region corresponding to one of aplurality of component layers with which transistors of the plurality ofbasic cells are formed and on lattice grids along which the plurality ofbasic cells are formed.

The third step includes the step of connecting one of the plurality ofcomponent layers and two of the plurality of signal wirings at thedetermined pin positions, in which two of the plurality of signalwirings are connected by the one component layer alone.

A semiconductor integrated circuit in which wirings are conducted inaccordance with one embodiment of the present invention includes twocontacts that connect one of a plurality of component layers with whichtransistors of a plurality of basic cells are formed and two of aplurality of signal wirings, wherein the two contacts are respectivelydisposed inside and outside of a region between a first power sourcewiring and a second power source wiring, and the two of the plurality ofsignal wirings are connected to one another by one of the componentlayers alone.

As a result, the signal wirings do not need to cross over the first andsecond power source wirings, and accordingly the wiring resource iseffectively utilized. Also, the wiring length of the signal wirings isshortened as compared to a conventional structure in which signal linescross over first and second power source wirings. Accordingly, one ofthe sources of signal delay can be eliminated. In accordance with oneembodiment of the present invention, one of the component layers otherthan layers in which first and second power source wirings are disposedis used also as a wiring material to cross the signal wirings over thefirst and second power source wirings and connect them to one another.

In one embodiment, the one component layer may be a diffusion layer. Ifa Ti silicide is formed on a surface of the diffusion layer, thediffusion layer has a substantially low sheet resistance and can be usedas a wiring material.

In this case, in the first step, a plurality of effective pin positionsdefined at positions on the diffusion layer may preferably be providedinside and outside the region between the first power source wiring andthe second power source wiring. Further, in the first step, effectivepin positions may be defined at all of the intersections of latticegrids on the diffusion layer. As a result, a wider range is secured inthe selection of positions of contacts, and spaces are secured forpassing signal wirings from other basic cells.

The basic cell includes a plurality of P-type transistors and aplurality of N-type transistors. The basic cell may be formed in asplit-gate type in which a gate layer is provided for each of theplurality of P-type transistors and N-type transistors.

In this instance, in the first step, an effective pin position definedfor each of the gate layers is provided in each of the areas inside andoutside the region between the first power source wiring and the secondpower source wiring. As a result, for example, the gate of the P-typetransistor is connected to the signal wiring in the area outside theregion between the first power source wiring and the second power sourcewiring, and the gates of the P-type transistor and the N-type transistorcan be connected in the area within the region.

The basic cell includes a plurality of P-type transistors and aplurality of N-type transistors. The basic cell may be formed in acommon-gate type in which a common gate layer is provided for theplurality of P-type transistors and N-type transistors.

In this instance, in the first step, an effective pin position definedfor each of the common gate layers is provided in an area inside theregion between the first power source wiring and the second power sourcewiring, and another effective pin position is provided at each end ofthe common gate layer outside the region.

As a result, for example, a signal wiring to the first gate or thesecond gate can be connected to a contact that is disposed outside theregion between the first and second power source wirings, and a signalwiring that crosses over the first and second power source wirings isnot required.

In a placing and routing method in accordance with another embodiment ofthe present invention, the first step includes the step of defining theeffective pin positions inside and outside a region between the firstpower source wiring and the second power source wiring, in a regioncorresponding to a gate layer of each of transistors that form theplurality of basic cells and on lattice grids along which the pluralityof basic cells are disposed.

A master slice type semiconductor integrated circuit designed accordingto the method has:

a substrate having a plurality of basic cells formed in a matrixthereon,

first and second power source wirings that are formed along a firstdirection and traverse the plurality of basic cells,

a plurality of signal wirings that are formed along the first directionor a second direction that traverses the first direction to provideconnections within each of the plurality of basic cells and/or betweenthe plurality of basic cells, and

a contact that connects one of gate layers of transistors that form oneof the plurality of basic cells to one of the plurality of signalwirings in an area outside a region between the first power sourcewiring and the second power source wiring.

In accordance with the method and the circuit designed by the method,one of the gate layers of transistors that form one of the plurality ofbasic cells can be connected to one of the plurality of signal wiringsby a contact disposed outside the region between the first power sourcewiring and the second power source wiring. In this case, a signal wiringto the gate can be connected to the contact that is disposed outside theregion between the first power source wiring and the second power sourcewiring, and therefore a signal wiring that crosses over the first andsecond power source wirings is not required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of definitions for effective pin positions ina master slice that has basic cells arranged in a matrix in accordancewith one embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along a line D-D′ of FIG. 1.

FIG. 3 is a circuit routing diagram of a placing and routing example fora semiconductor integrated circuit that is designed based on librarydata including the definitions of effective pin positions shown in FIG.1.

FIG. 4 is a logic circuit diagram of a logic circuit realized by thecircuit routing of FIG. 3.

FIG. 5 is a flow chart illustrating steps of an automatic placing androuting process.

FIG. 6 is a schematical illustration of definitions for effective pinpositions in which the present invention is implemented in a common gatetype basic cell in accordance with one embodiment of the presentinvention.

FIG. 7 is an illustration of a conventional wiring pattern of a logiccircuit that has the same function as that of the logic circuit havingthe wiring pattern shown in FIG. 3.

BEST MODE OF EMBODIMENT OF THE INVENTION

Embodiments of the present invention will be described below withreference to the accompanying drawings.

Definitions for Effective Pin Positions

FIG. 1 shows definitions for positions of contacts (effective pinpositions) on a master slice 100 having basic cells 110 that arearranged in a matrix. It is noted that FIG. 1 shows only one of basiccells 110. FIG. 1 also shows lattice grids 120. All of the positions ofthe pins and wiring routes are determined on the lattice grids 120 by anautomatic placing and routing apparatus.

The basic cell 110 shown in FIG. 1 has two P-type MOS transistors 111and 112 and two N-type MOS transistors 113 and 114. The structure of thetransistors 111-114 will be described with reference to FIG. 2 thatshows a cross-sectional view taken along a line D-D′ of FIG. 1.

A P-type well 130 is formed in a forming region where the N-type MOStransistors 113 and 114 are formed. The P-type MOS transistors 111 and112 have polysilicon layers 140 and 141 that function as gates, and aP-type diffusion region 142 that becomes either a source or a drain.Similarly, the N-type MOS transistors 113 and 114 have polysiliconlayers 150 and 151 that function as gates and a P-type diffusion region152 that becomes either a source or a drain.

Referring to FIG. 2 which illustrates a cross section taken along theline D-D′ of FIG. 1, an SiO₂ film (not shown) that functions as a gateinsulation film is formed under the polysilicon layer 140. Similarly,the N-type MOS transistors 113 and 114 have SiO₂ films (not shown).

In the description below, the N-type diffusion region 142 is dividedinto three regions by channel regions immediately below the gates. Thesethree regions are respectively referred to as a first diffusion region(for example, a source) 142A, a second diffusion region (for example, acommon drain) 142B and a third diffusion region (for example, a source)142C. Three regions of the P-type diffusion region 152 are also referredto as a first diffusion region 152A, a second diffusion region 152B anda third diffusion region 152C.

A plurality of the basic cells 110 each having the above-describedstructure are formed and an insulation layer 160 shown in FIG. 2 isformed thereon to manufacture the master slice 100.

Then, a plurality of metal wiring layers are provided on the masterslice 100 to realize a circuit function required by the user. To providethe metal wiring layers, an automatic placing and routing apparatus isused to determine placement and routing of the plurality of wiringlayers and pins (contacts and vias).

The automatic placing and routing apparatus determines placement androuting of the plurality of wiring layers and pins based on definitionsfor effective pin positions registered in a library and a net list thatdefines definitions for connections between the basic cells.

Referring to FIG. 1, definitions for effective pin positions of contactsregistered in the library are shown on the master slice 100. Theeffective pin positions are those for input pins and output pins to beconnected to signal wirings and power source pins to be connected topower source wirings. FIG. 1 also shows for reference a first powersource wiring 170 that is set at a potential VDD and a second powersource wiring 171 that is set at a potential VSS.

In the description below, pin definition sections illustrated by squaresin FIG. 1 are presented with coordinates on lattice grids. In FIG. 1,not all of the pin definition sections are presented with coordinates.However, for example, a pin definition A2 refers to a pin definitionsection that is located at an intersection of a vertical line A and alateral line 2.

As shown in FIG. 1, the polysilicon layers 140, 141, 150 and 151 thatfunction as gates are provided with pin definition sections A1, C1, A7,C7, A8, C8, A14 and C14. The first pin definition sections A7, C7, A8and C8 are disposed within a region defined between the two first andsecond power source wirings 170 and 171. On the other hand, the secondpin definition sections A1, C1, A14 and C14 are disposed outside theregion that is defined between the two first and second power sourcewirings 170 and 171.

As shown in FIG. 1, five pin definition sections A2-A6 and five pindefinition sections A9-A13 are provided in the first diffusion regions142A and 152A, respectively. Among these pin definition sections, thepin definition sections A5, A6, A9 and A10 are disposed within theregion that is defined between the two first and second power sourcewirings 170 and 171. The pin definition sections A4 and A11 are disposedat locations overlapping the first and the second power source wirings,respectively. The pin definition sections A2, A3, A12 and A13 aredisposed outside the region that is defined between the two first andsecond power source wirings 170 and 171.

Similarly, as shown in FIG. 1, five pin definition sections each,namely, B2-B6, B9-B13 C2-C6 and C9-C13, are provided in the seconddiffusion regions 142B and 152C and the third diffusion regions 142C and152C, respectively.

In the example shown in FIG. 1, pin definition sections are provided onall of the locations at which the first—third diffusion regions142A-142C and 152A-152C overlap the intersections of the lattice grids.However, those of the pin definition sections that are not expected tobe required may be deleted. However, power source pin definitionsections among the plurality of pin definition sections need to bedisposed at locations that overlap the first power source wiring 170 orthe second power source wiring 171, and input pin definition sectionsand output pin definition sections may preferably be disposed inside andoutside a region defined between the two first and second power sourcewirings 170 and 171. In contrast, effective pin positions that are notfrequently used are the pin definition sections B4 and B11 that aredisposed at locations overlapping the first and second power sourcewirings 170 and 171 over the second diffusion regions 142B and 152B.However, when the second diffusion regions 142B and 152B are used assources, the pin definition sections B4 and B11 need to be defined.

Automatic Placing and Routing

An automatic placing and routing apparatus uses the definitionsdescribed above and performs a process for placing and routing the basiccells within a semiconductor integrated circuit. The process will bedescribed with reference to a flow chart shown in FIG. 5.

First, all definitions for positions of pins (contacts, vias andexternal terminals) including the pin definition sections describedabove are registered in a library (step 1), and the library is inputtedin the automatic placing and routing apparatus (step 2). Further, a netlist that defines connections between the basic cells is inputted (step3). Then, placing and routing of pins with respect to the master sliceshown in FIG. 1 are determined (step 4). Automatic routing in step 4 isconducted according to a priority wiring direction that is determinedfor each of the layers.

Definitions for effective pin positions are registered in a library instep 1 of FIG. 5. One example of the registered definitions is shown inTable 1 below. Coordinates shown in FIG. 1 are coordinates on latticegrids shown in FIG. 3.

TABLE 1 PIN DEFINITIONS TYPE OBJECT COORDINATES P First Gate A1, A7 MSecond Gate C1, C7 O First Diffusion Region A2-A6 S Second DiffusionRegion B2-B6 Third Diffusion Region C2-C6 N First Gate A8, A14 M SecondGate C8, C14 O First Diffusion Region A9-A13 S Second Diffusion RegionB9-B13 Third Diffusion Region C9-C13

The pin definitions shown in Table 1 indicate that any one of the pinslisted in Table 1 can be optionally selected when wirings are determinedaccording to the net list.

Embodiment Example of Semiconductor Integrated Circuit

FIG. 3 shows one example of placement and routing for a semiconductorintegrated circuit that is designed based on the library data, includingthe definitions for the effective pin positions described above, andFIG. 4 shows its logic circuit.

The circuit shown in FIG. 3 provides a logic circuit shown in FIG. 4.The logic circuit has two inverters 310 and 320, a NAND gate 330 inwhich outputs from the inverters 310 and 320 are inputted, and aninverter 340 that inverts an output from the NAND gate 330.

Each of the two inverters 310 and 320 is respectively formed with one ofthe basic cells in a first basic cell column 300A, shown in FIG. 3. TheNAND gate 330 is formed with one of the basic cells in a second basiccell column 300B, shown in FIG. 3. The inverter 340 is formed with oneof the basic cells in the first basic cell column 300A, shown in FIG. 3.

It is noted that wirings shaded with hatching shown in FIG. 3, are metalwiring layers in a first layer, and their priority wiring directionextends in a transverse direction. Wirings shaded with cross-hatching,shown in FIG. 3, are metal wirings in a second layer, and their prioritywiring direction extends in a vertical direction.

The first basic cell column 300A, shown in FIG. 3, has first and secondpower source wirings 170A and 171A formed with the first metal wiringlayers along the transverse direction. The second basic cell column 300Balso has first and second power source wirings 170B and 171B formed withthe first metal wiring layers along the transverse direction.

The first power source wiring 170A and the inverters 310, 320 and 340are connected to each other through a contact formed at the pindefinition section B4, shown in FIG. 1.

The second power source wiring 171A and the inverters 310, 320 and 340are connected to each other through a contact formed at the pindefinition section B11, shown in FIG. 1.

Gates 141 and 151 of P-type and N-type MOS transistors in the firstbasic cell column 300A that form the inverters 310, 320 and 340 areconnected to one another through contacts formed at the pin definitionsections C7 and C8, shown in FIG. 1, and a signal wiring 400 formed withthe first metal wiring layer. (In FIG. 3, reference numerals are addedonly for the inverter 310.)

Also, the diffusion regions 142C and 152C of the P-type and N-type MOStransistors in the first base cell column 300A that compose theinverters 310, 320 and 340 are connected to each other through contactsformed at pin definition sections C6 and C9, shown in FIG. 1, and asignal wiring 401 formed with the first metal wiring layer. (In FIG. 3,reference numerals are added only for the inverter 310.)

The first power source wiring 170B and the NAND gate 330 are connectedto each other through contacts formed at the pin definition sections A4and C4, shown in FIG. 1.

The second power source wiring 171B and the NAND gate 330 are connectedto each other through a contact formed at the pin definition sectionA11, shown in FIG. 1.

Gates 140 and 150 of the P-type and N-type MOS transistors in the secondbasic cell column 300B that forms the NAND gate 330 are connected toeach other through contacts formed at the pin definition sections A7 andA8, shown in FIG. 1, and a signal wiring 402 formed with the first metalwiring layer.

Similarly, gates 141 and 151 of the P-type and N-type MOS transistors inthe second basic cell column 300B that forms the NAND gate 330 areconnected to each other through contacts formed at the pin definitionsections C7 and C8, shown in FIG. 1, and a signal wiring 403 formed withthe first metal wiring layer.

Further, the second and third diffusion regions 142B and 152C of theP-type and N-type MOS transistors in the second basic cell column 300Bthat forms the NAND gate 330 are connected to each other throughcontacts formed at the pin definition sections B6 and C9, shown in FIG.1, and a signal wiring 404 formed with the first metal wiring layer. Thesignal wiring 404 is an output line of the NAND gate 330.

Also, the basic cells in the first and second basic cell columns 300Aand 300B that form the NAND gate 330 and the inverter 340 are connectedto each other through a wiring group 405, consisting of a contact formedat the pin definition section C14, shown in FIG. 1, a signal wiringformed with the first metal wiring layer, a via, a signal wiring formedwith the second metal wiring layer, a via, a signal wiring formed withthe first metal wiring layer and a contact formed at the pin definitionsection B2, shown in FIG. 1.

Next, signal wirings among the inverter 310 and 320 and the NAND gate330 will be described.

An output signal from the inverter 310 is inputted in the NAND gate 330through a wiring group 406, consisting of a contact formed at the pindefinition section C12, shown in FIG. 1, the first layer signal wiring,a via, the second layer signal wiring, a via, the first layer signalwiring and a contact formed at the pin definition section A1, shown inFIG. 1.

An output signal from the inverter 320 is inputted in the NAND gate 330through a wiring group 407, consisting of a contact formed at the pindefinition section C13, shown in FIG. 1, the first layer signal wiring,a via, the second layer signal wiring, a via, the first layer signalwiring and a contact formed at the pin definition section C1, shown inFIG. 1.

Comparison with Conventional Wiring Pattern

FIG. 7 shows a conventional wiring pattern of a logic circuit that hasthe same function of the logic circuit having the wiring pattern shownin FIG. 3.

By comparing FIG. 3 with FIG. 7, the following differences between thesewiring patterns are observed.

First, the wiring pattern in FIG. 3 does not have any wiring thatcrosses the first and second power source wirings 170A, 171A, 170B and171. In contrast, in the wiring pattern in FIG. 7, five signal lines500-504, formed with the second metal wiring layers, cross the firstand/or second power source wirings 171A and 170B.

Secondly, the wiring length of each of the signal wirings that connectthe inverters 310 and 320 to the NAND gate 330, shown in the wiringpattern in FIG. 7, is substantially longer than that of the wiringpattern shown in FIG. 3.

It is understood from the above that the conventional wiring patternshown in FIG. 7 wastes the wiring resource of the second metal wiringlayer. Also, since the wiring length of the second metal wiring layer ofthe wiring pattern shown in FIG. 7 is particularly long, its wiringcapacitance and wiring resistance increase. As a consequence, problemsof signal delays occur with the advancement of the miniaturizedmanufacturing process that further narrows the wiring width. Each of thesignal wirings that connect the inverters 310 and 320 to the NAND gate330 is continuous from one end to the other end. In contrast, each ofthe corresponding signal wirings in FIG. 3 is divided into sections.

For example, no metal wiring exists between the signal wirings 401 and406 that is connected to the inverter 310 shown in FIG. 3. As a result,the third diffusion region 152C of the N-type MOS transistor that isconnected to the signal wirings 401 and 406 is also used as a wiringmaterial. Also, the third diffusion region 152C of the N-type MOStransistor in the first basic cell column 300A that forms the inverters320 and 340 is used as a wiring material.

Similarly, the signal wirings 404 and 405 in the basic cell in thesecond basic cell column 300B that forms the NAND gate 330 are connectedto each other through the second diffusion region 142B that functions asa wiring material.

Further, for example, in the basic cell in the second basic cell column300B that forms the NAND gate 330, a signal is inputted in the gates 140and 150 of the P-type and N-type MOS transistors through a contactprovided at an end of the gates 140 and 150 that are disposed invertical alignment with one another. This is different from the wiringpattern shown in FIG. 7 in which a signal is inputted at a sectiongenerally intermediate of the gates 140 and 150 that are disposed invertical alignment with one another. Therefore, the wiring pattern shownin FIG. 3 effectively uses the gates 140 and 150 as wiring materials.

It is noted that the present invention is not limited to the embodimentsdescribed above, and a variety of modifications can be made within thescope of the subject matter of the present invention.

For example, the present invention is not only applicable to split-gatetype basic cells, but also applicable to common-gate type basic cells.The present invention is applicable to placement and routing for masterslices that have a variety of basic cells mounted thereon.

FIG. 6 is an illustration of definitions for effective pin positionswhen the present invention is applied to common-gate type basic cells.Table 2 below shows the definitions for effective pin positions shown inFIG. 6.

TABLE 2 PIN DEFINITIONS TYPE OBJECT COORDINATES P First Gate A1, A7 MSecond Gate C1, C7 O First Diffusion Region A2-A6 S Second DiffusionRegion B2-B6 Third Diffusion Region C2-C6 N First Gate A7, A13 M SecondGate C7, C13 O First Diffusion Region A8-A12 S Second Diffusion RegionB8-B12 Third Diffusion Region C8-C12

In Table 2 above, the definitions for effective pin positions of thefirst gate of the P-type MOS transistor and the first gate of the N-typeMOS transistor commonly use the coordinate A7. Similarly, thedefinitions for effective pin positions of the second gate of the P-typeMOS transistor and the second gate of the N-type MOS transistor commonlyuse the coordinate C7.

Further, the present invention is applicable to a stackable wiringmethod in which contacts overlap vias as viewed in a plan view. In thiscase, the use of a stackable wiring method is effective when the firstand second power source wirings 170A and 171A are formed with the secondmetal wiring layers.

What is claimed is:
 1. A design method for designing a master slicesemiconductor integrated circuit, having a placing and wiring method fora mater slice type semiconductor integrated circuit conducted by anautomatic placing and routing apparatus with respect to a master slicehaving a plurality of basic cells formed in a matrix, in which first andsecond power source wirings that are formed along a first direction antitraverse the plurality of basic cells connected to a plurality of signalwirings that are formed along the first direction or a second directionthat traverses the first direction to provide connectons within each ofthe plurality of basie cells and/or between the plurality of basiccells, the design method comprising: a first step of registering, in theautomatic placing and routing apparatus that defines the first directionor the second direction as a priority wiring direction for each oflayers in which the wirings are formed, definitions of effective pinpositions that connect the plurality of signal wirings, the plurality offirst and second power source wirings, and the plurality of basic cells;a second step of registering a net list that defines connections amongthe plurality of basic cells in the automatic placing and routingapparatus; and a third step of determining placement of actual pinpositions and wiring routes for the first and second power sourcewirings and the plurality of signal wirings, based on data of thedefinitions of the effective pin positions and the net list, wherein thefirst step includes the step of defining the effective pin positionsinside and outside a region between the first power source wiring andthe second power source wring, in a region corresponding to one of aplurality of component layers with which transistors of the plurality ofbasic cells are formed, and on lattice grids along which the pluralityof basic cells are formed, and wherein the third step includes the stepof connecting one of the plurality of component layers and two of theplurality of signal wirings at determined pin positions, in which thetwo of the plurality of signal wirings are connected by the onecomponent layer.
 2. A design method for designing a master slice typesemiconductor integrated circuit according to claim 1, wherein the onecomponent layer is a diffusion layer.
 3. A design method for designing amaster slice type semiconductor integrated circuit according to claim 2,wherein the first step includes the step of providing a plurality of theeffective pin positions defined at positions on the diffusion layer,both inside and outside the region between the first power source wiringand the second power source wiring.
 4. A design method for designing amaster slice type semiconductor integrated circuit according to claim 2,wherein the first step defines effective pin positions at all of theintersections of lattice grids on the diffusion layer.
 5. A designmethod for designing a master slice type semiconductor integratedcircuit according to any one of claim 2 through claim 4, wherein thebasic cell includes a plurality of P-type transistors and a plurality ofN-type transistors, and the basic cell is formed m a split-gate type inwhich a gate layer is provided for each of the plurality of P-typetransistors and N-type transistors.
 6. A design method for designing amaster slice type semiconductor integrated circuit according to claim 5,wherein, in the first step, an effective pin position defined for eachof the gate layers is provided in each of areas inside and outside theregion between the first power source wiring and the second power sourcewiring.
 7. A design method for designing a master slice typesemiconductor integrated circuit according to any one of claim 2 throughclaim 4, wherein the basic cell includes a plurality of P-typetransistors and a plurality of N-type transistors, and the basic cell isformed in a common-gate type in which a common gate layer is providedfor the plurality of P-type transistors and N-type transistors.
 8. Adesign method for designing a master slice type semiconductor integratedcircuit according to claim 7, wherein, in the first step, an effectivepin position defined for each of the common gate layers is provided inan area inside the region between the first power source wiring and thesecond power source wiring, and another effective pin position isprovided at each end of the common gate layer outside the region.
 9. Adesign method for designing a master slice semiconductor integratedcircuit, including a placing and wiring method for a mater slice typesemiconductor integrated circuit conducted by an automatic placing androuting apparatus with respect to a master slice having a plurality ofbasic cells formed in a matrix, in which first and second power sourcewirings that are formed along a first direction and traverse theplurality of basic cells connected to a plurality of signal wirings thatare formed along the first direction or a second direction thattraverses the first direction to provide connections within each of theplurality of basic cells and/or between the plurality of basic cells,the design method comprising: a first step of registering, in theautomatic placing and routing apparatus that defines the first directionor the second direction as a priority wiring direction for each oflayers in which the wirings are formed, definitions of effective pinpositions that connect the plurality of signal wirings, the plurality offirst and second power source wirings, and the plurality of basic cells;a second step of registering a net list that defines connections amongthe plurality of basic cells in the automatic placing and routingapparatus; and a third step of determing placement of actual pinpositions and wiring routes for the first and second power sourcewirings and the plurality of signal wirings, based on data of thedefinitions of the effective pin positions and the net list, wherein thefirst step includes the step of defining the effective pin positionsinside and outside a region between the first power source wiring andthe second power source wring, in a region corresponding to a gate layerof each of the transistors that form the plurality of basic cells, andon lattice grids along which the plurality of basic cells are disposed.